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description the CXA1998AQ is an ic developed for analog signal processing in tape recorders. processing for both the recording and playback systems is achieved on one chip. features 11-bit serial data interface recording/playback mute function recording equalizer gp and fp can be adjusted externally. agc (automatic gain control) comparator for ams (automatic music sensor) recording/playback equalizer amplifier with 1.7 times speed switching absolute maximum ratings (ta = 25?) supply voltage v cc , v dd 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 645 mw operating conditions supply voltage v cc 6.5 to 10.0 v v dd 4.5 to 5.5 v structure bipolar silicon monolithic ic applications all analog signal processing in the cassette decks of tape recorders and compact music centers applicable head applicable to mitsumi electric co., ltd. playback head: bp-7442-cp-6973 recording/playback head: bc-9242-cb-9267 ?1 CXA1998AQ e96802a78 recording/playback equalizer amplifier sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic)
?2 CXA1998AQ block diagram and pin configuration (top view) d1 d2 d3 d4 d5 d6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 37 38 39 40 41 42 43 44 45 46 47 48 mute agc gain 19.5db 10k 40k receq ams gnd gnd gnd v dd v dd 20k 20k 20k 20k d11 d9 d10 d8 gnd d7 gnd d11 gnd d9 gnd gnd gnd gnd gnd gnd v dd gnd 40k agc gain 19.5db 10k receq iref 36 35 34 33 gnd rfs 2.8v 210k gnd gnd 210k gnd 210k 210k gnd 2.8v agc agc off a eq b eq pbeq ctl receq ctl deck a/b speed shift registers latches gp cal a eq b eq agc tc agc in1 rec in1 agc out1 rec out1 ams gain ams gnd ams tc ams out pbmute rmutei rmute speed bpa bpb pl1 pl2 m1 m2 v dd latch rfc vcc vg gnd agc in2 rec in2 agc out2 rec out2 dgnd xreset data clk fp cal pb out1 pb fb21 pb fb11 pb inb1 pb ina1 pb ina2 pb inb2 pb fb12 pb fb22 pb out2 iref
?3 CXA1998AQ pin description pin no. 1 symbol dc voltage i/o equivalent circuit description gp cal 1.2v connects a resistor for determining the high-band peak gain of recording equalizer. reference setting resistance is 27k . i/o resistance 2 a eq ? deck a equalizer switch. low: 120s eq high: 70s eq 3 b eq 2.5v (open) i deck b equalizer switch. low: normal tape, 120s eq medium: cro 2 tape, 70s eq high: metal tape, 70s eq 53k 4 agc tc 0.0v connects a resistor and capacitor for determining agc attack/recovery time constants. 1 vcc vcc gnd gnd 147 2 30k v cc 147 gnd gnd v cc 2 v cc 147 50k v cc gnd gnd 5k 5k 3 v cc gnd gnd v cc 2 200 100k 500 500 2 147 2 4 200 5k 4 (ta = 25?, v cc = 8v, v dd = 5v, no signal, reset on)
?4 CXA1998AQ 5 32 agc in1 agc in2 4.0v i agc signal input. input resistance changes between 50k and 100k . agc functions when the signal of ?0dbm or more is input to agc for agc on. (external 47f//300k for pin 4) 50k 6 31 rec in1 rec in2 4.0v i recording equalizer input. 50k 7 30 agc out1 agc out2 4.0v o agc output. 147 8 29 rec out1 rec out2 4.0v o recording equalizer output. 147 v cc 147 40k 500 10 v cc gnd gnd 3 500 2 5p 8 29 v cc 147 18752 500 4 v cc gnd vgs gnd 2 500 7 30 107423 9945 vgs v cc 147 50k v cc gnd vgs 23186 1759 vgs gnd 6 31 v cc 147 10k 40k 4 v cc gnd vgs 5 32 pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?5 CXA1998AQ ams block ground. 9 ams gain 3.5v connects a resistor for determining ams signal detection level and a capacitor for determining hpf cut- off frequency. 10 ams gnd 0.0v 12 ams out 8.0v o ams output. no signal detection: high signal detection: low 11 ams tc 8.0v connects time constant for ams detection. v cc 147 gnd v cc gnd 100k 10 9 11 vcc gnd 1k gnd 147 vcc vcc gnd vcc 12 vcc vcc 10k gnd 10 gnd pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?6 CXA1998AQ 13 pbmute 14 rmute1 5.0v connects a capacitor for setting time constant for playback mute on/off switching. 15 rmute output for recording mute on/off switch control signal. outputs d11 from pin 26 (data). 16 speed 5.0v o output for recording/playback equalizer speed switch control signal. outputs d9 from pin 26 (data). low: normal speed high: high speed (1.7 times) 17 bpa 5.0v o outputs d6 from pin 26 (data). 18 bpb outputs d5 from pin 26 (data). 19 pl1 outputs d4 from pin 26 (data). 20 pl2 outputs d3 from pin 26 (data). 21 m1 outputs d2 from pin 26 (data). 22 m2 outputs d1 from pin 26 (data). 23 v dd power supply of serial data interface block. 5.0v 13 14 v dd v dd 20k 20k gnd 4 147 gnd gnd connects a capacitor for setting time constant for recording mute on/off switching. 4 v dd 5k gnd gnd v dd 4 5k 20k 15 16 4 v dd gnd gnd v dd 4 10k 20k 17 18 19 20 21 22 v dd 23 pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?7 CXA1998AQ 24 latch 27 xreset ? serial data interface latch input. 25 data i serial data interface reset input. low: reset. at this time serial data outputs (pins 15 to 22) are all open (high). 26 serial data interface clock input. serial data interface serial data input. 28 dgnd 0.0v serial data interface block ground. clk 2k gnd v dd 10.5k 25a gnd 30k 5p 4 30k 24 27 4k gnd v dd 10.5k 25a gnd 30k 4 30k 25 26 gnd 28 33 gnd 0.0v ground. 35 v cc 8.0v power supply. 34 vg 4.0v signal reference voltage. connects a capacitor for ripple rejection. 60k gnd 33 34 v cc 147 45k 30k 4 v cc gnd gnd 500 500 2 30k 2 to each vgs 35 v cc pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?8 CXA1998AQ connects a resistor (12k ) for determining equalizer gains. 36 rfc 8.0v connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. 37 iref 38 47 pb out2 pb out1 2.8v o playback equalizer output. 147 48 fp cal 1.2v connects a resistor for determining the high- band peak frequency of recording equalizer. reference setting resistance is 27k . 36 v cc 147 v cc gnd 3 250 3 to each rfs vcc gnd 2 gnd 37 48 147 5p vcc vcc gnd vcc 3 500 147 6 gnd 15p 47 38 500 39 46 pb fb22 pb fb21 2.8v connects a capacitor for determining playback equalizer time constants, such as 120s and 70s. 39 46 v cc 147 3 gnd 2k 2k gnd gnd 4 7k 3 4 rfs pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?9 CXA1998AQ 40 45 pb fb12 pb fb11 1.4v playback equalizer negative feedback. 105k 41 42 43 44 pb inb2 pb ina2 pb ina1 pb inb1 0.0v i playback equalizer input. 70k 41 42 43 44 45 70k 10p v cc gnd v cc gnd 6 v cc 40 gnd 1k 1k 210k 210k v cc rfs 2 10k 5k 6 147 30p 147 note) ams gnd (pin 10), dgnd (pin 28) and gnd (pin 33) are each independent in the ic and are not connected. be sure tp ground each of the ground pins listed above. the resistance of open collector outputs (pins 15 to 22) can be connected vcc. pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?10 CXA1998AQ electrical characteristics (ta = 25?, v cc = 8.0v, v dd = 5.0v, refer to electrical characteristics measurement circuit) item operating voltage current consumption measurement conditions min. typ. max. unit v cc v dd sum of v cc and v dd pin currents norm ?ns, no signal pin 4 external r300k //c47f f = 1khz, vin = ?5dbm pin 4 external r300k //c47f f = 1khz, vin = ?5dbm pin 4 external r300k //c47f f = 1khz, vin = 0dbm pin 4 external r300k //c 47f f = 1khz, vin = ?5dbm pin 9 external r9.1k , c0.015f pin 11 external r100k //c0.1f f = 5khz, 0db = ?1dbm (at pbeq reference output level) f = 315hz, vin = ?0dbm reference for frequency response f = 2.7khz, vin = ?8.5dbm at 120s ?ns, 315hz f = 4.5khz, vin = ?3.8dbm at 120s ?ns, 315hz f = 5.3khz, vin = ?2.5dbm at 120s ?ns, 315hz f = 9.1khz, vin = ?7.8dbm at 120s ?ns, 315hz 120s ?ns, r l = 2.7k f = 1khz, thd + n = 1% 120s ?ns, r l = 2.7k f = 1khz, vin = ?6.4dbm 120s ?ns, rg = 470 ??weighting filter 120s ?ns, rg = 470 , playback mute off 120s ?ns, f = 1khz, vin = ?1.4dbm agc on output level agc on channel balance agc on distortion agc off output level no signal detection threshold level 120s ?ns frequency response 120s ?ns frequency response 70s ?ns frequency response 120s ?hs frequency response 70s ?hs frequency response signal handling total harmonic distortion s/n ratio output offset voltage playback mute characteristics 6.5 4.5 13.5 ?3.0 ?.0 ?.5 ?1.5 ?3.0 ?.1 ?.1 1.8 2.1 ?0.0 55.0 2.4 8.0 5.0 19.7 ?1.0 0.0 0.3 ?.5 ?.2 ?1.0 1.3 1.7 3.0 3.6 ?.0 0.3 62.0 2.7 ?00 10.0 5.5 25.0 ?.0 2.0 1.5 ?.5 ?9.0 2.9 2.9 4.8 5.1 0.7 3.2 ?0 v v ma dbm db % dbm db dbm db dbm % db v db agc ams playback equalizer amplifier block
?11 CXA1998AQ reference input level reference output level channel balance norm ?ns frequency response norm ?ns frequency response norm ?ns frequency response cro 2 ?ns frequency response cro 2 ?ns frequency response cro 2 ?ns frequency response metal ?ns frequency response metal ?ns frequency response metal ?ns frequency response norm ?hs frequency response norm ?hs frequency response norm ?hs frequency response cro 2 ?hs frequency response cro 2 ?hs frequency response cro 2 ?hs frequency response metal ?hs frequency response metal ?hs frequency response metal ?hs frequency response db norm ?ns, 315hz, input level at which reference output can be obtained norm ?ns, 315hz norm ?ns, 315hz, output level difference 1ch-2ch for ?6.7dbm input f = 3khz at norm ?ns, 315hz, reference output ?0db f = 8khz at norm ?ns, 315hz, reference output ?0db f = 12khz at norm ?ns, 315hz, reference output ?0db f = 3khz at norm ?ns, 315hz, reference output ?0db f = 8khz at norm ?ns, 315hz, reference output ?0db f = 12khz at norm ?ns, 315hz, reference output ?0db f = 3khz at norm ?ns, 315hz, reference output ?0db f = 8khz at norm ?ns, 315hz, reference output ?0db f = 12khz at norm ?ns, 315hz, reference output ?0db f = 5khz at norm ?ns, 315hz, reference output ?0db f = 15khz at norm ?ns, 315hz, reference output ?0db f = 20khz at norm ?ns, 315hz, reference output ?0db f = 5khz at norm ?ns, 315hz, reference output ?0db f = 15khz at norm ?ns, 315hz, reference output ?0db f = 20khz at norm ?ns, 315hz, reference output ?0db f = 5khz at norm ?ns, 315hz, reference output ?0db f = 15khz at norm ?ns, 315hz, reference output ?0db f = 20khz at norm ?ns, 315hz, reference output ?0db ?6.7 ?0.0 0.0 ?.6 5.2 11.7 4.9 11.4 17.6 5.9 10.2 15.2 0.2 9.7 14.9 6.4 16.2 19.7 8.0 15.5 19.4 ?8.2 ?.5 ?.8 3.4 8.7 3.7 9.9 14.8 4.7 8.7 12.9 ?.6 7.6 11.9 5.2 14.1 16.7 6.8 13.7 16.9 ?5.2 1.5 0.6 7.0 14.7 6.1 12.9 20.4 7.1 11.7 17.5 2.2 11.8 17.4 7.6 18.3 22.7 9.2 17.3 21.9 dbm recording equalizer amplifier block item measurement conditions min. typ. max. unit
?12 CXA1998AQ norm ?ns, r l = 2.7k f = 1khz, thd + n = 1% norm ?ns, r l = 2.7k f = 1khz, 0db norm ?ns, rg = 5.1k ??weighting filter norm ?ns norm ?ns, f = 1khz 8db a-eq (pin 2) a-eq (pin 2) b-eq (pin 3) b-eq (pin 3) b-eq (pin 3) signal handling total harmonic distortion s/n ratio output offset voltage recording mute characteristics 8.0 57.0 3.6 0.0 2.5 0.0 2.2 4.2 8.8 0.2 60.6 4.0 ?00 0.5 4.4 ?0 0.5 v cc 0.5 2.8 v cc db % db v control voltage low level 1 control voltage high level 1 control voltage low level 2 control voltage medium level 1 control voltage high level 2 note) norm ?ns: normal tape ?normal speed norm ?hs: normal tape ?high speed cro 2 ?ns: cro 2 tape ?normal speed cro 2 ?hs: cro 2 tape ?high speed metal ?ns: metal tape ?normal speed metal ?hs: metal tape ?high speed 120s ?ns: eq = 120s ?normal speed 120s ?hs: eq = 120s ?high speed 70s ?ns: eq = 70s ?normal speed 70s ?hs: eq = 70s ?high speed db v recording equalizer amplifier block item measurement conditions min. typ. max. unit
?13 CXA1998AQ v il (latch/clk/data/xreset) (pins 24, 25, 26, 27) v ih (latch/clk/data/xreset) (pins 24, 25, 26, 27) v ol , i ol = 2ma (max) (pins 15, 16, 17, 18, 19, 20, 21, 22) i oz leak current which flows to the output pin when i oz output is open; applied voltage is 10v. (pins 15 to 22) (1) f ck (2) t wc (3) t wr (4) t sdk (data ? clk) (5) t hcd (clk ? data) (6) t wd (7) t sld (latch ? data) (8) t hcl (clk ? latch) (9) t hlc (latch ? clk) low level input voltage high level input voltage low level output voltage high level output off leak current maximum clock frequency minimum clock pulse width minimum reset pulse width minimum data setup time minimum data hold time minimum data pulse width minimum latch setup time minimum latch hold time minimum clock hold time 0.0 3.5 0.0 500 1.5 v dd 0.5 1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 note) v dd is cpu supply voltage of 5.0v. v cc is 10.0v for high level output off-leak current. the threshold levels of low level input voltage and high level input voltage depend on v dd . input level detection is done by comparison with v dd /2. (refer to equivalent circuit?of pin description.) ? v ? khz item measurement conditions min. typ. max. unit 11-bit serial data interface block
?14 CXA1998AQ timing chart for 11-bit serial data interface (v dd = 5.0v) t wc t wc t wd t hcd t sdk 1.5v 3.5v d1 d2 1.5v 3.5v 1.5v t sld 3.5v 1.5v 3.5v 1.5v t hcl d10 d11 t hlc t wr clk data latch clk data latch xreset
?15 CXA1998AQ electrical characteristics measurement circuit 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 37 39 46 47 48 36 35 34 gp cal a eq b eq agc tc agc in1 rec in1 agc out1 rec out1 ams gain ams gnd ams tc ams out pbmute rmutei rmute speed bpa bpb pl1 pl2 m1 m2 v dd latch rfc vcc vg gnd agc in2 rec in2 agc out2 rec out2 dgnd xreset data clk fp cal pb out1 pb fb21 pb fb11 pb inb1 pb ina1 pb ina2 pb inb2 pb fb12 pb fb22 pb out2 iref r114 10k r103 2.2k s36a s36b r113 10k r102 2.2k s35a s35b r112 10k r101 2.2k s34a s34b r111 r100 2.2k s33b r110 r99 2.2k s32b r109 r98 2.2k s31b 10k s33a 10k s32a 10k s31a r108 r97 2.2k s30b 10k s30a r107 r96 2.2k s29b 10k s29a r106 c34 0.1 s57a 10k s53 r105 s57b 10k s54 c33 0.1 s56b s56a s58h s58g s58f s58e s58d s58c s58b s58a 23 5v 5v latch 2.2 /25v c30 2.7k r86 s12d 4.7 /25v c28 10k r79 0.47 /50v c26 0.47 /50v c22 10k r89 s27b 100 r84 s27a 100 r81 s21b r76 390k r72 47k s21a 5.1k 32 33 10k r61 47 /25v c18 8v 47 /25v c17 47 /25v c15 1k r5b s15 clk data xreset 38 40 100 r44 47 /25v c10 4.7k r37 470 r50 41 0.018 c14 1 c9 4.7 /25v c4 82k r35 470 r49 1 c8 4.7 /25v c3 82k r34 470 r48 1 c7 4.7 /25v c2 82k r33 470 r47 1 c6 4.7 /25v c1 82k r32 42 43 44 100 r43 47 /25v c5 4.7k r36 0.018 c13 45 2.2 /25v c11 2.7k r38 s12b 27k r42 2.2 /25v 2.7k s12a 12k r45 100 r41 s11a 10k r52 s11b 2.2 /25v c29 2.7k r85 s12c 10k r88 s26b 100 r83 s26a 4.7 /25v c27 10k r78 s22b 0.47 /25v c25 r74 s25b r73 390k r71 47k r80 100 0.47 /50v c21 5.1k s22a 5.1k r68 300k r66 4 5 47 /25v c20 3 s20 s19 s18 metal cro2 norm 10k r63 10k r59 2 4.2v 2.5v 0.5v 27k r56 1 9.1k r90 0.015 c31 9 10 0.1 c32 100k r92 100k r93 10k r94 s28 gnd dc output tl072 + 600 r30 att s5b s5a 6db att s4b s4a 9db att s3b s3a 17db att s2b s2a 29db att s1b s1a 40db ac input charge1 charge2 10k r51 100 r40 s10b s10a 1khz band pass filter (20db) audio (22.2hz ?22.2khz) filter "a" weighting filter 30db amp buf s505 s504 s503 s502 s501 ac output 100k r536 gnd 4.7k r54 10k r64 s16 5.1k r69 c24 0.1 s25a r75 c23 0.1 s14 r39 c12 0.1 c16 120 s 70 s s9 s8 s7 s6 s13 s55 s23 0.1 c19 b eq a eq s17 s37 s24
?16 CXA1998AQ application circuit gp cal a eq b eq agc tc agc in1 rec in1 agc out1 rec out1 ams gain ams gnd ams tc ams out pbmute rmutei rmute speed bpa bpb pl1 pl2 m1 m2 v dd latch rfc vcc vg gnd agc in2 rec in2 agc out2 rec out2 dgnd xreset data clk fp cal pb out1 pb fb21 pb fb11 pb inb1 pb ina1 pb ina2 pb inb2 pb fb12 pb fb22 pb out2 iref v dd 100k v dd v dd 47k v dd 47k v dd 47k v dd 47k v dd 47k v dd 47k v dd 47k v dd 47k gnd 0.1 gnd 22 100k 100k 0.1 2.2k 0.1 gnd 27k v cc 3.3meg 47 0.47 0.1 2.7k 4.7 10k 2.2 2.2 10k gnd gnd gnd gnd v cc v cc gnd 27k 47 100 gnd 0.018 47 100 gnd 0.018 2.2 10k gnd gnd 12k 100k gnd 100k gnd 100k gnd v dd 2.2 gnd 2.2 gnd 0.1 2.7k 4.7 10k 0.47 gnd gnd 47 gnd 47 gnd 100 1k v cc bias osc gnd deck-a pb-head gnd gnd r/p-head deck-b gnd 150p 820p 10k 180p 12mh gnd 150p 180p 12mh 820p 10k d1 d2 d3 d4 d5 d6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 37 38 39 40 41 42 43 44 45 46 47 48 mute agc gain 19.5db 10k 40k receq ams gnd gnd gnd v dd v dd 20k 20k 20k 20k d11 d9 d10 d8 gnd d7 gnd d11 gnd d9 gnd gnd gnd gnd gnd gnd v dd gnd 40k agc gain 19.5db 10k receq iref 36 35 34 33 gnd rfs 2.8v 210k gnd gnd 210k gnd 210k 210k gnd 2.8v agc agc off a eq b eq pbeq ctl receq ctl deck a/b speed shift registers latches rec pb rec pb application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?17 CXA1998AQ 1. system control mode playback and recording equalizer (1) playback equalizer (120s/70s) deck-ab (serial data d10 (pin 25)) a-eq (pin 2) b-eq (pin 3) l h l m/h l h 120s (deck a) 70s (deck a) according to a-eq control 120s (deck b) 70s (deck b) according to b-eq control (3) recording equalizer (normal, cro 2 , metal) b-eq (pin 3) rec mode l normal (type i ) m cro 2 (type ii ) h metal (type iv ) (4) recording mute (pin 14) on/off control is performed by 11-bit serial data interface d11 (pin 26). a fader function is achieved using a time constant circuit formed with the external capacitor and incorporated 20k resistor. (5) fp cal (pin 48) the standard resistor setting is 27k , but when resistance value is larger, fo (hz) is lower, and when resistance value is smaller, fo (hz) is higher. (fo: high-band peak frequency) (6) gp cal (pin 1) the standard resistor setting is 27k , but when resistance value is larger, high-band peak gain is larger, and when resistance value is smaller, high-band peak gain is smaller. (2) playback mute (pin 13) on/off control is performed by 11-bit serial data interface d7 (pin 26). a capacitor for setting the switching time constant is connected. time constant = 20k c
?18 CXA1998AQ 2. 11-bit serial data interface d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 m2 m1 pl2 pl1 bpb bpa pb mute agc off speed deck ab rec mute pin 22 pin 21 pin 20 pin 19 pin 18 pin 17 pin 16 pin 15 low low low low low low low mute off agc function stops low, normal speed deck a selected low mute off high (open) high (open) high (open) high (open) high (open) high (open) high mute on agc function operates high (open) 1.7 deck b selected high (open) mute on output pin input set at low input set at high output data (pin 26) control signal d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 clk (pin 25) data (pin 26) latch (pin 24) xreset (pin 27) d11 the data signal is taken in at the rising edge of the clk signal. the data signal is taken into the internal shift register when the latch signal is low. (outputs (pins 15 to 22) hold the previous value while the latch signal is low.) the internal shift register data is latched and output in parallel at the rising edge of the latch signal. (internal shift register data is loaded while the latch signal is high.) the clk signal of the 11th bit should fall after the latch signal rises. reset is done when the xreset pin is low. (asynchronous method) outputs (pins 15 to 22) are all high (open) during reset.
?19 CXA1998AQ make sure that v dd is 4.0v or more and xreset is 1.5v or less, and 1s or more when resetting by applying cr time constant to xreset (pin 27) and turning power on. 1s or more 1.5v or less 4.0v or more v dd (pin 23) xreset (pin 27) a 1s or more 5.0v 4.0v or more v dd (pin 23) xreset (pin 27) 0v xreset (pin 27) input level detection is done by comparison with v dd /2. the level should be v dd /2 > xreset during the interval a. for resetting with cpu when power is turned on examples of agc control during timer recording (1) resets when power is turned on (agc function operates). (2) agc is turned off after agc inputs (pins 5 and 32) rise. (external capacitor charge of agc tc is discharged.) (3) agc is turned on and timer recording begins.
?20 CXA1998AQ d11 h l d10 h l d9 h l d8 h l d12 h l d13 h l d14 h l d15 h l 6 xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (1) xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (2) xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (3) xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (4) y3 a3 b3 y4 a4 b4 v dd v ss y2 b2 a2 y1 b1 a1 74hc00 y3 a3 b3 y4 a4 b4 v dd v ss y2 b2 a2 y1 b1 a1 74hc08 (2) y3 a3 b3 y4 a4 b4 v dd v ss y2 b2 a2 y1 b1 a1 74hc08 (1) y4 a4 y5 a5 y6 a6 v dd v ss y3 a3 y2 a2 y1 a1 74hc04 r5 10k on off start 3 on off reset c5 0.1 4 c12 0.1 c9 0.1 c8 0.1 r3 10k r6 10k c4 0.1 18 c14 0.1 c13 0.1 c20 0.1 5 13 100 r16 12 7 14 q1 clock reset q9 q8 q10 q11 v dd v ss q2 q3 q4 q7 q5 q6 q12 74hc4040 xa2 b2 xres2 xq2 q1 c1 r/c1 v dd v ss r/c2 c2 q2 xq1 xres1 b1 xa1 74hc123 b0 a0 b1 a1 a2 b2 a3 v dd v ss a < bout a = bout a > bout a > bin a = bin a < bin b3 74hc85 xload ena 1 reset q9 q8 q10 q11 v dd v ss ena p dd dc db da clock xreset 74hc161 qh serial in a b c d clk2 v dd v ss xqh h g f e clk1 s/xl 74hc165 (1) c19 0.1 c18 0.1 1 2 4 8 h l h l h l h l d4 h l d5 h l d6 h l d7 h l qh serial in a b c d clk2 v dd v ss xqh h g f e clk1 s/xl 74hc165 (2) c17 0.1 c11 0.1 c10 0.1 d3 h l d2 h l d1 h l 8 17 68k r17 11 c16 4.7 c15 1000p r13 2.2k 1 r7 220 r8 220 r15 220 r14 220 r11 10k r12 10k 9 16 r1 1m r2 220 c6 15p c7 15p 4.4mhz r4 220 r9 220 2 latch clk data xreset dgnd 5v sw gnd gnd 100 /25v c21 15 10 19 100 r18 dgnd exclk c3 0.1 c2 0.1 c 0.1 exclk 250khz 500khz 100 r19 100 r10 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 1 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 15 16 circuit diagram for 11-bit serial data transfer evaluation tool
?21 CXA1998AQ timing chart for 11-bit serial data transfer evaluation tool dummy d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 2s count reset clock stop (14) reset/clock stop and count reset (15) data hc165 (16) clk (17) = (8) (18) (19) latch (13) (12) (11) hc123 (10) h when a = b (9) (8) clk gate cont. (7) s/l (6) = (4) (5) (4) (3) start pulse (2) clk (1) clk the numbers (1) to (19) correspond to those of test pins for the 11-bit serial data transfer evaluation tool circuit.
?22 CXA1998AQ detection status ams out (pin 12) signal detection low no signal detection high pb out1 pb out2 20k 20k sa lpf det 25khz 100k gnd v cc v cc v cc gnd ams gnd ams out ams tc c1 r1 r2 c2 r3 hpf ams gain inside ic 9 11 12 10 f c g 10 1khz 25khz 100khz gain (db) f (hz) 3. ams (1) ams output logic ams out (pin 12) is an open collector output pin. when a 3.9 k resistor is connected to v cc = 8v: low: approximately 0.5v (i ol = 2ma (max.)) high: 8v fig. 1 shows the ams block diagram. fig. 1. ams block diagram fig. 2 shows the frequency response of the signal output from hpf. fig. 2. frequency response
?23 CXA1998AQ (2) ams level setting the ams level is set by adjusting hpf gain and cut-off frequency with the external resistor and capacitor at pin 9. g and fc in fig. 2 are obtained from the following formula. g = 20log (1 + 100k/r1) [db] (1) fc = 1 / (2 ? ?c1 ?r1) [hz] full-wave rectifier is applied for the signal at det. signal detection time is set by the time constant of pin 11 external resistor and capacitor. det signal detection level: = ?.5dbm (typ.) = playback equalizer reference output level + ams level + hpf gain (2) playback equalizer reference output level of ?1dbm is 0db. ex.) to set ams level at ?5db, determine and set the constant for pin 9 external resistor. (calculate assuming pbout1 = pbout2) first, get the required hpf gain from formula (2). ?.5dbm = ?1dbm + (?5db) + hpfgain, so hpf gain = 38.5db. next, get pin 9 external resistance from formula (1). 38.5db = 20log (1 + 100k / r1), so r1 1.2k , and external resistance is 1.2k .
?24 CXA1998AQ example of representative characteristics quiescent current consumption vs. supply voltage v cc ?supply voltage [v] quiescent current consumption [ma] 6 15 11 78910 25 16 17 18 19 20 21 22 23 24 i cc is the sum of the v cc and v dd currents. v dd = 5.0v pb in pb fb1 pb fb2 pb out playback equalizer frequency response frequency [hz] 65 60 55 50 45 40 35 30 25 gain [db] 20 50 100 200 500 1k 2k 5k 10k 20k 50k 120s ?ns 120s ?hs 70s ?ns 70s ?hs m v cc = 8v 0.018 470 10f 47 100 2.2
?25 CXA1998AQ recording equalizer frequency response frequency [hz] output response [db] 20 0 100 50 200 1k 500 2k 10k 5k 20k 50k 2 4 6 8 10 12 14 16 18 20 22 24 26 28 recording equalizer frequency response frequency [hz] output response [db] 20 0 100 50 200 1k 500 2k 10k 5k 20k 50k 2 4 6 8 10 12 14 16 18 20 22 24 26 28 (tape) (speed) norm ? ns cro 2 ? ns metal? ns v cc = 8v 0db = norm ?ns, 315hz, ?0dbm (tape) (speed) norm ? ns cro 2 ? ns metal? ns v cc = 8v 0db = norm ?ns, 315hz, ?0dbm
?26 CXA1998AQ ams quiescent detection level frequency response frequency [hz] 30 25 20 15 10 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 ?0 ams input level (playback equalizer output level) [db] 20 50 100 200 500 1k 2k 5k 10k 20k 50k v cc = 8v 120s ?ns ams out 8v 0db = ?1dbm, 315hz (playback equalizer reference output level) a b a: pin 9 r9.1k c0.015 b: pin 9 r1k c0.1 ams gain ams tc ams out 0.1 100k 100k to 8v a : 0.015 9.1k b : 0.1 1k 9 11 12 agc output characteristics agc tc 47 300k v cc = 8v 1khz agc off agc on 10 5 0 ? ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?0 ? input level [dbm] output level [dbm] 4
?27 CXA1998AQ recording equalizer total harmonic distortion output level [dbm] t.h.d + noise [%] ?5 10 05 0.1 0.2 0.5 1.0 2.0 v cc = 8v norm ?ns r l = 2.7k w 1khz 0db = ?0dbm ?0 ? playback equalizer total harmonic distortion output level [dbm] t.h.d + noise [%] ?0 ? ?5 ?0 0.1 0.2 0.5 1.0 2.0 v cc = 8v 120s ?ns r l = 2.7k w 1khz ?5 ?0
?28 CXA1998AQ package outline unit: mm sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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